The present invention generally relates to dynamic random access memory (DRAM), and in particular to a method for updating DRAM and a system using the same.
DRAM is a type of semiconductor memory whose principle is to represent whether a binary bit is 1 or 0 by utilizing whether an electron is stored in a capacitor. Since real capacitors leak charge, it causes insufficiency for the potential difference which makes the memory fade. This phenomenon requires the capacitor to be charged periodically on a regular basis to ensure the memory is preserved forever. Because of this character of requiring periodical refresh, it is referred to as “dynamic”, as opposed to static random access memory (SRAM), in which the memory would never fade even if it is not refreshed as long as the data is stored.
Compared to SRAM, the advantage of DRAM is its structural simplicity. Only one capacitor and one transistor are required per bit to process the data, while six transistors are required per bit in SRAM. DRAM has a smaller area than SRAM under the same storage bits. DRAM also has a very high density. The higher the capacity in a cell volume lowers the cost. However, DRAM has the disadvantage of slow access speed and greater power consumption. Like most of random access memory (RAM), it is also a volatile memory device since it loses its data immediately when power is removed.
DRAM has to be refreshed in the retention time due to leakage current. When a conflict occurs between a refresh operation and a normal access operation (e.g., read or write operation), the normal access operation has to be suspended until the refresh operation is completed. DRAM is composed of a plurality of banks. Each bank includes a plurality of rows. In each clock period, one row of the banks is refreshed. Meanwhile, other banks can be accessed, but only the refreshed bank cannot be accessed. Continued access for a given bank would be interrupted by its refresh operation, particularly for a bank being continually accessed for a long time, reducing access throughput.
U.S. Pat. No. 6,954,387 B2, “DYNAMIC RANDOM ACCESS MEMORY WITH SMART REFRESH SCHEDULER”, proposed a refresh method for improving the access throughput by using a flag bit register being shifted up/down. The application proposed a refresh method for a configurable DRAM. However, for the bank being continually accessed for a long time, the access throughput is still lower in above method. It is difficult to meet requirements for applications by using the existing DRAM refresh method and system with respect to some of the applications requiring a higher access throughput.